Area-time-efficient VLSI residue-to-binary converters
Srikanthan, T., Bhardwaj, M. and Clarke, C. T., 1998. Area-time-efficient VLSI residue-to-binary converters. IEE Proceedings - Computers and Digital Techniques, 145 (3), pp. 229-235.
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The authors present highly area-time-efficient VLSI implementations of residue reverse converters called compressed multiply accumulate (CMAC) converters. This efficiency results from carefully identifying and eliminating redundancy in existing proposals. Specifically, the partial sum generation and addition are merged into a single carry-save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The CMAC reverse converters proposed here were fabricated in a 0.8 μm N-well CMOS process. Due to the techniques mentioned, the resulting VLSI implementation was 3-4 times smaller than recently reported results, while delivering identical throughput and achieving four times lower delay. The AT2 efficiency of these converters O(n2log3n) equals the best known to date. Comprehensive analysis of the various implementation options (CPA, CLA or serial) presented will be of great value to the VLSI system designer in choosing a reverse converter that conforms to the delay, area and power requirements imposed by a given application
|Creators||Srikanthan, T., Bhardwaj, M. and Clarke, C. T.|
|Uncontrolled Keywords||cmos process,arithmetic codes,power requirements,residue number systems,vlsi,single carry-save addition operation,adders,addition,compressed multiply accumulate converters,partial sum generation,area,analogue-digital conversion,area-time-efficient vlsi residue-to-binary converters,delay,vlsi implementations|
|Departments||Faculty of Engineering & Design > Electronic & Electrical Engineering|
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