Implementing area-time efficient VLSI residue to binary converters
Srikanthan, T., Bhardwaj, M. and Clarke, C. T., 1997. Implementing area-time efficient VLSI residue to binary converters. In: IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97), 1997-11-05, Leicester.
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In this paper, the authors present highly area-time efficient VLSI implementations of residue reverse converters called Compressed Multiply ACcumulate (CMAC) converters. The efficiency results from identifying and eliminating redundancy in previously reported designs. Specifically, the partial sum. Generation and addition are merged into a single carry save addition operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The analysis of the various implementation options (CPA, CLA or serial) presented here will aid system designers in choosing a reverse converter that conforms to the time, area and power requirements imposed by a given application
|Item Type||Conference or Workshop Items (Paper)|
|Creators||Srikanthan, T., Bhardwaj, M. and Clarke, C. T.|
|Uncontrolled Keywords||binary converters,area-time efficient,module multipliers,cmac,digital signal processing chips,carry save addition,residue number systems,reverse converter,vlsi,compressed multiply accumulate,residue reverse converters,convertors|
|Departments||Faculty of Engineering & Design > Electronic & Electrical Engineering|
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