Current mode techniques for multiple valued arithmetic and logic
Clarke, C. T., Nudd, G. R. and Summerfield, S., 1994. Current mode techniques for multiple valued arithmetic and logic. In: IEEE International Symposium on Circuits and Systems (ISCAS '94), 1994-05-30 - 1994-06-02, London.
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This paper analyses the general properties of Current Mode Multiple Valued Logic (CMMVL) circuits, and presents a framework for further exploitation. A unified circuit view is proposed in which circuits are described in terms of CMMVL to voltage mode binary decoders, and binary to CMMVL encoders. The relative merits of various encodings are explored for a single digit multiplier. It is shown that CMMVL has an inherent advantage in the VLSI layout of fan-in dominated subsystems such as Wallace trees. The construction of CMMVL circuit cells for general logic is discussed
|Item Type||Conference or Workshop Items (Paper)|
|Creators||Clarke, C. T., Nudd, G. R. and Summerfield, S.|
|Uncontrolled Keywords||binary to cmmvl encoders, decoders, current mode techniques, vlsi, logic design, multivalued logic circuits, adders, multiple valued logic, digital arithmetic, mvl circuits, vlsi layout, multiple valued arithmetic, integrated logic circuits, cmmvl circuit cells, wallace trees, decoding, multiplying circuits, current mode multiple valued logic, single digit multiplier, encoding, fan-in dominated subsystems|
|Departments||Faculty of Engineering & Design > Electronic & Electrical Engineering|
|Additional Information||Vol 4|
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