Instruction set customization for area-constrained FPGA designs

Reference:

Prakash, A., Lam, S.-K., Clarke, C. T. and Srikanthan, T., 2011. Instruction set customization for area-constrained FPGA designs. In: Proceedings - IEEE International SOC Conference, SOCC 2011. Piscataway, NJ: IEEE Computer Society, pp. 329-334. (International System on Chip Conference)

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Official URL:

http://dx.doi.org/10.1109/SOCC.2011.6085114

Abstract

Custom instructions are commonly used to meet the strict design constraints in high performance systems. This paper extends the application space of our previously proposed FPGA-aware custom instruction enumeration and selection technique for area-constrained designs that maximizes the logic utilization of the available FPGA space. Results indicate a factor of 4 improvement in cycle savings over conventional selection techniques and an average runtime reduction of over 31% and 50% in the enumeration and selection phases respectively.

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