Research

Instruction set customization for area-constrained FPGA designs


Reference:

Prakash, A., Lam, S.-K., Clarke, C. T. and Srikanthan, T., 2011. Instruction set customization for area-constrained FPGA designs. In: 24th IEEE International System on Chip Conference, SOCC 2011, September 26, 2011 - September 28, 2011, 2011-01-01, Taipei, Taiwan. Piscataway, NJ: IEEE Computer Society, pp. 329-334. (International System on Chip Conference)

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Abstract

Custom instructions are commonly used to meet the strict design constraints in high performance systems. This paper extends the application space of our previously proposed FPGA-aware custom instruction enumeration and selection technique for area-constrained designs that maximizes the logic utilization of the available FPGA space. Results indicate a factor of 4 improvement in cycle savings over conventional selection techniques and an average runtime reduction of over 31% and 50% in the enumeration and selection phases respectively.

Details

Item Type Conference or Workshop Items (UNSPECIFIED)
CreatorsPrakash, A., Lam, S.-K., Clarke, C. T. and Srikanthan, T.
DOI10.1109/socc.2011.6085114
DepartmentsFaculty of Engineering & Design > Electronic & Electrical Engineering
StatusPublished
ID Code28156
Additional Information24th IEEE International System on Chip Conference, SOCC 2011. 26-28 September 2011. Taipei, Taiwan.

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