Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration


Lam, S.-K., Clarke, C.T. and Srikanthan, T., 2014. Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. ACM Transactions on Reconfigurable Technology and Systems, 7 (3), 26.

Related documents:

PDF (Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration) - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader
Download (373kB) | Preview

    Official URL:

    Related URLs:


    Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the performance benefits of reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework achieves this by: (1) providing a means for choosing suitable custom instruction selection heuristics, (2) leveraging FPGA-awaremerging of custom instructions to maximize the reconfigurable logic block utilization in each configuration, and (3) incorporating a hierarchical loop partitioning strategy to reduce runtime reconfiguration overhead. We show that the performance gain can be improved by employing suitable custom instruction selection heuristics that, in turn, depend on the reconfigurable resource constraints and the merging factor (extent to which the selected custom instructions can be merged). The hierarchical loop partitioning strategy leads to an average performance gain of over 31% and 46% for full and partial runtime reconfiguration, respectively. Performance gain can be further increased to over 52% and 70% for full and partial runtime reconfiguration, respectively, by exploiting FPGA-aware merging of custom instructions.


    Item Type Articles
    CreatorsLam, S.-K., Clarke, C.T. and Srikanthan, T.
    Related URLs
    URLURL Type
    DepartmentsFaculty of Engineering & Design > Electronic & Electrical Engineering
    Research CentresCentre for Advanced Sensor Technologies (CAST)
    ?? WIRC ??
    Publisher StatementExploiting_FPGA_Aware_Merging_of_Custom_Instructions_for_Runtime_Reconfiguration.pdf: © ACM, 2014. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Issue on 11th International Conference on Field-Programmable Technology (FPT'12) and Special Issue on the 7th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC'12), Volume 7, Issue 3, August 2014.
    ID Code41645


    Actions (login required)

    View Item

    Document Downloads

    More statistics for this item...