Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators
Clarke, C. T. and Srikanthan, T., 2004. Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators. In: 38th Asilomar Conference on Signals, Systems and Computers, 2004-11-07 - 2004-11-10, California.
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The use of correlators to detect pseudo random number sequences is widespread, and forms the basis of pervasive technologies such as GPS. The correlation function is subject to a trade-off between hardware cost and speed. In this paper we present a residue arithmetic based technique that can create a pseudo random number sequence correlator that has both low hardware cost and high speed.
|Item Type||Conference or Workshop Items (Paper)|
|Creators||Clarke, C. T.and Srikanthan, T.|
|Uncontrolled Keywords||hardware reduction,pseudorandom sequence correlators,global positioning system,residue number systems,pseudonoise codes,residue arithmetic techniques,random sequences,gps,correlators|
|Departments||Faculty of Engineering & Design > Electronic & Electrical Engineering|
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