Research

ARM/THUMB code compression for embedded systems


Reference:

Xu, X. H., Jones, S. R. and Clarke, C. T., 2003. ARM/THUMB code compression for embedded systems. In: 15th International Conference on Microelectronics (ICM 2003), 2003-12-09 - 2003-12-11, Cairo.

Related documents:

This repository does not currently have the full-text of this item.
You may be able to access a copy if URLs are provided below.

Official URL:

http://dx.doi.org/10.1109/ICM.2003.1287715

Abstract

The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. In this paper we propose a new memory compression architecture, which employs a lossless data compression algorithm to achieve a further size reduction of around 20% on the THUMB code. We show that in some applications, the decompression can be performed in software on the main system processor without excessive processing time overheads.

Details

Item Type Conference or Workshop Items (Paper)
CreatorsXu, X. H., Jones, S. R. and Clarke, C. T.
DOI10.1109/ICM.2003.1287715
Uncontrolled Keywordssize reduction, memory compression architecture, embedded systems, data compression, risc, memory architecture, data compression algorithm, reduced instruction set computing
DepartmentsFaculty of Engineering & Design > Electronic & Electrical Engineering
RefereedNo
StatusPublished
ID Code5996

Export

Actions (login required)

View Item