Hierarchical fault diagnosis of analog integrated circuits

Reference:

Ho, C. K., Shepherd, P. R., Eberhardt, F. and Tenten, W., 2001. Hierarchical fault diagnosis of analog integrated circuits. IEEE Transactions on Circuits and Systems. Part I: Fundamental Theory and Applications, 48 (8), pp. 921-929.

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Official URL:

http://dx.doi.org/10.1109/81.940182

Abstract

This paper introduces a hierarchical-fault-diagnosis algorithm as an aid to testing analog and mixed signal circuits. The diagnosis approach is based on that introduced by Wey and others and makes use of the self-test algorithm, and the component-connection model. The main extension to these techniques is the use of a hierarchical approach whereby blocks of circuitry are grouped together leading to a reduction in matrix size, so making even large scale circuits diagnosable. Other improvements from this approach include a novel test-point selection procedure and the fact that hard faults can also be diagnosed, provided they lie completely within a hierarchical block. The overall algorithm is described and the results from example circuits show good functionality of the diagnosis algorithm. Fault masking and sensitivity to the simulation/measurement resolution of test point values are examined and are highlighted as future activities to further improve the approach

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