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Items by Clarke, Christopher

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Number of items: 58.

Wong, L. C. C., Jolly, P., Clarke, C. T. and Estrela, P., 2014. Enhanced label-free DNA hybridisation detection using Open Circuit Potential measurement with gold nanoparticles. In: 24th Anniversary World Congress on Biosensors, 2014-05-27 - 2014-05-30, Melbourne.

Betts, D., Bowen, C.R., Kim, H.A., Gathercole, N., Clarke, C.T. and Inman, D.J., 2013. Nonlinear dynamics of a bistable piezoelectric-composite energy harvester for broadband application. European Physical Journal - Special Topics, 222 (7), pp. 1553-1562.

Prakash, A., Lam, S.-K., Clarke, C.T. and Srikanthan, T., 2013. FPGA-aware techniques for rapid generation of profitable custom instructions. Microprocessors and Microsystems, 37 (3), pp. 259-269.

Wong, L. C. C., Clarke, C. and Estrela, P., 2013. Label-free biosensor arrays using open circuit potential measurements. In: 3rd International Conference on Bio-Sensing Technology, 2013-05-11 - 2013-05-14, Sitges.

Betts, D.N., Bowen, C.R., Kim, H.A., Gathercole, N., Clarke, C.T. and Inman, D.J., 2013. Investigation of bistable piezo-composite plates for broadband energy harvesting. Proceedings of SPIE, 8688, 86881N.

Al-Shueli, A., Clarke, C. T., Donaldson, N. and Taylor, J. T., 2013. Improved signal processing methods for velocity selective neural recording using multi-electrode cuffs. IEEE Transactions on Biomedical Circuits and Systems

Prakash, A., Lam, S.-K., Srikanthan, T. and Clarke, C. T., 2013. Modelling communication overhead for accessing local memories in hardware accelerators. In: 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE, pp. 31-34.

Prakash, A., Srikanthan, T. and Clarke, C.T., 2012. Custom instructions with local memory elements without expensive DMA transfers. In: 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. IEEE, pp. 647-650.

Wang, D., Clarke, C.T. and Evans, A., 2012. Examination of the concept of a row-column separated median filter. In: 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. IEEE, pp. 659-662.

Rieger, R., Taylor, J. and Clarke, C., 2012. Signal processing for velocity selective recording systems using analogue delay lines. In: ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. IEEE, pp. 2195-2198.

Al-shueli, A., Clarke, C. T. and Taylor, J. T., 2012. Simulated nerve signal generation for multi-electrode cuff system testing. In: Proceedings - 2012 International Conference on Biomedical Engineering and Biotechnology, iCBEB 2012. , pp. 892-896.

Taylor, J., Schuettler, M., Clarke, C. T. and Donaldson, N., 2012. The theory of velocity selective neural recording: a study based on simulation. Medical and Biological Engineering and Computing, 50 (3), pp. 309-318.

Lam, S. K., Srikanthan, T. and Clarke, C.T., 2012. Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. In: ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings. IEEE.

Lam, S. K., Srikanthan, T. and Clarke, C. T., 2011. Architecture-aware technique for mapping area-time efficient custom instructions onto FPGAs. IEEE Transactions on Computers, 60 (5), pp. 680-692.

Taylor, J., Schuettler, M., Clarke, C. and Donaldson, N., 2011. A summary of the theory of velocity selective neural recording. In: 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS 2011, 2011-08-30 - 2011-09-03, Boston, MA.

Prakash, A., Lam, S.-K., Clarke, C. T. and Srikanthan, T., 2011. Instruction set customization for area-constrained FPGA designs. In: Proceedings - IEEE International SOC Conference, SOCC 2011. Piscataway, NJ: IEEE Computer Society, pp. 329-334. (International System on Chip Conference)

Lam, S. K., Srikanthan, T. and Clarke, C. T., 2009. Selecting profitable custom instructions for area-time-efficient realization on reconfigurable architectures. IEEE Transactions on Industrial Electronics, 56 (10), pp. 3998-4005.

Clarke, C. T., Xu, X., Rieger, R., Taylor, J. and Donaldson, N., 2009. An implanted system for multi-site nerve cuff-based ENG recording using velocity selectivity. Analog Integrated Circuits and Signal Processing, 58 (2), pp. 91-104.

Clarke, C. T., Taylor, J. T. and Xu, X., 2008. Analogue/digital interface and communications aspects in a multi-channel ENG recording asic. In: IEEE International Symposium on Circuits and Systems (ISCAS 2008), 2008-05-18 - 2008-05-21, Seattle, WA.

Xu, X. H., Clarke, C. T. and Taylor, J. T., 2008. Multi-site nerve cuff based implantable system for wide bandwidth ENG signal recording. In: 2nd International Conference on Signal Processing and Communication Systems (ICSPCS 2008), 2008-12-15 - 2008-12-17, Gold Coast.

Sathyanarayana, S., Srikanthan, T. and Clarke, C. T., 2007. Real Time Tracking of Camera Motion through Cylindrical Passages. In: 15th International Conference on Digital Signal Processing, 2007-07-01 - 2007-07-04, Cardiff, Wales.

Clarke, C., 2006. A Method and Apparatus For Correlating Data Sequences. G01S1/00-WO2006048676 (A1), 11 May 2006.

Vivekanandarajah, K., Srikanthan, T. and Clarke, C. T., 2006. Profile directed instruction cache tuning for embedded systems. In: IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2006-03-02 - 2006-03-03, Karlsruhe.

Suchitra, S., Lam, S. K., Clarke, C. T. and Srikanthan, T., 2006. Accelerating rotation of high-resolution images. IEE Proceedings - Vision Image and Signal Processing, 153 (6), pp. 815-824.

Lam, S. K., Srikanthan, T. and Clarke, C. T., 2006. Rapid generation of custom instructions using predefined dataflow structures. Microprocessors and Microsystems, 30 (6), pp. 355-366.

Durga, P. and Clarke, C., 2006. System-On-Chessboard: A rapid SOC implementation. In: 2006 IASTED Conference on Advances in Computer Science and Technology, 2006-01-23 - 2006-01-25, Puerto Vallarta.

Rieger, R., Schuettler, M., Pal, D., Clarke, C., Langlois, P., Taylor, J. and Donaldson, N., 2006. Very low-noise ENG amplifier system using CMOS technology. IEEE Transactions on Neural Systems and Rehabilitation Engineering, 14 (4), pp. 427-437.

Rieger, R., Taylor, J., Clarke, C., Pal, D., Langlois, P. and Donaldson, N., 2005. 10-channel very low-noise ENG amplifier system using CMOS technology. In: IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2005-05-23 - 2005-05-26, Kobe.

Clarke, C., Taylor, J., Rieger, R. and Donaldson, N., 2005. A distributed neural sensor system. In: IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2005-05-23 - 2005-05-26, Kobe.

Suchitra, S., Sneha, S., Srikanthan, T. and Clarke, C., 2005. Elimination of sign precomputation in flat CORDIC. In: IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2005-05-23 - 2005-05-26, Kobe.

Kwan, P. C. and Clarke, C. T., 2005. FPGAs for improved energy efficiency in processor based systems. In: Advances in Computer Systems Architecture. Vol. 3740. Berlin: Springer, pp. 440-449. (Lecture Notes in Computer Science)

Lam, S., Srikanthan, T., Clarke, C. and Low, H., 2004. Achieving hardware-efficient neural network based pattern recognition system through linear approximation. In: 38th Asilomar Conference on Signals, Systems and Computers, 2004-11-07 - 2004-11-10, California.

Vivekanandarajah, K., Srikanthan, T., Clarke, C. T. and Bhattacharyya, S., 2004. A novel static prediction scheme for filter cache structures. IEICE Transactions on Electronics, E87C (4), pp. 543-548.

Clarke, C., Qiang, L., Peremans, H. and Muller, R., 2004. An FPGA based bio-mimetic implementation of neural signal processing in bats. In: IoA Symposium on Bio-sonar Systems & Bio-Acoustics, 2004-09-14 - 2004-09-16, Loughborough.

Clarke, C. T. and Qiang, L., 2004. Bat on an FPGA: a biomimetic implementation of a highly parallel signal processing system. In: 38th Asilomar Conference on Signals, Systems and Computers, 2004-11-07 - 2004-11-10, California.

Qiang, L. and Clarke, C., 2004. Digital neuromorphic processing for a simplified algorithm of ultrasonic reception. The Journal of the Acoustical Society of America (JASA), 115 (5), p. 2518.

Clarke, C. T., Qiang, L., Peremans, H. and Hernandez, A., 2004. FPGA implementation of a neuromimetic cochlea for a bionic bat head. In: Field Programmable Logic and Application. Vol. 3203. Berlin: Springer, pp. 1073-1075. (Lecture Notes in Computer Science)

Xu, X., Clarke, C. and Jones, S., 2004. High performance code compression architecture for the embedded ARM/THUMB processo. In: Computing Frontiers, 2004-04-14 - 2004-04-16, Ischia.

Clarke, C. T. and Srikanthan, T., 2004. Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators. In: 38th Asilomar Conference on Signals, Systems and Computers, 2004-11-07 - 2004-11-10, California.

Xu, X. H., Jones, S. R. and Clarke, C. T., 2003. ARM/THUMB code compression for embedded systems. In: 15th International Conference on Microelectronics (ICM 2003), 2003-12-09 - 2003-12-11, Cairo.

Vivekanandarajah, K., Srikanthan, T., Clarke, C. T. and Bhattacharyya, S., 2003. Static pattern predictor (SPP) based low power instruction cache design. In: International Conference on Embedded Systems and Applications (ESA03), 2003-06-23 - 2003-06-26, Las Vegas, NV.

Bhardwaj, M., Srikanthan, T. and Clarke, C. T., 1999. A reverse converter for the 4-moduli superset {2n-1, 2 n, 2n+1, 2n+1+1}. In: 14th IEEE Symposium on Computer Arithmetic, 1999-04-14 - 1999-04-16, Adelaide.

Bhardwaj, M., Srikanthan, T. and Clarke, C. T., 1999. VSLI costs of arithmetic parallelism: A residue reverse conversion perspective. In: 14th IEEE Symposium on Computer Arithmetic, 1999-04-14 - 1999-04-16, Adelaide.

Srikanthan, T., Gisuthan, B. and Clarke, C. T., 1998. A Framework for Computing scaling factors for Flat CORDIC. In: Symposium on High Performance Computing (HPC), 1998-10-23 - 1998-10-25, Singapore.

Srikanthan, T., Bhardwaj, M. and Clarke, C. T., 1998. Area-time-efficient VLSI residue-to-binary converters. IEE Proceedings - Computers and Digital Techniques, 145 (3), pp. 229-235.

Deodhar, A. A., Bhurdwaj, M., Clarke, C. T. and Srikanthan, T., 1998. Designing efficient residue arithmetic based VLSI correlators. In: IEEE International Conference on Acoustics, Speech and Signal Processing, 1998-03-12 - 1998-03-15, Seattle, WA.

Srikanthan, T., Bhardwaj, M. and Clarke, C. T., 1997. Implementing area-time efficient VLSI residue to binary converters. In: IEEE Workshop on Signal Processing Systems - Design and Implementation (SIPS 97), 1997-11-05, Leicester.

Srikanthan, T., Clarke, C. T., Lam, S. K. and Wee, L. C., 1997. Auto-Generator for FPGA-XILINX To VLSI-MAGIC Conversion. In: 7th International Symposium on IC Technology, Systems and Applications (ISIC-97), 1997-09-10 - 1997-09-12, Singapore.

Clarke, C. T. and Nudd, G. R., 1995. Highly Non-Linear Encoders For Current Mode Multiple-Valued Logic. In: 6th International Symposium on IC Technology, Systems & Applications (ISIC-95), 1995-09-06 - 1995-09-08, Singapore.

Clarke, C. T. and Nudd, G. R., 1995. Shallow Multiplication Circuits in VLSI. In: 6th International Symposium on IC Technology, Systems & Applications (ISIC-95), 1995-09-06 - 1995-09-08, Singapore.

Clarke, C. T. and Nudd, G. R., 1995. Three Dimensional CORDIC with Reduced Iteration. In: 6th International Symposium on IC Technology, Systems & Applications (ISIC-95), 1995-09-06 - 1995-09-08, Singapore.

Clarke, C. T., 1995. Unraveling CORDIC. In: 6th International Symposium on IC Technology, Systems & Applications (ISIC-95), 1995-09-06 - 1995-09-08, Singapore.

Clarke, C. T. and Nudd, G. R., 1994. Redundant Arithmetic CORDIC System with a Unit Scale Factor. In: McWirter, J. G., ed. Mathematics in Signal Processing III. Oxford: Oxford University Press, pp. 63-73.

Clarke, C. T., Nudd, G. R. and Summerfield, S., 1994. Current mode techniques for multiple valued arithmetic and logic. In: IEEE International Symposium on Circuits and Systems (ISCAS '94), 1994-05-30 - 1994-06-02, London.

Nudd, G. R., Papefstathiou, E., Papay, Y., Atherton, T. J., Clarke, C. T., Kerbyson, D. J., Stratton, A. F., Ziani, R. and Zemerly, M. J., 1993. A Layered Approach to the Characterisation of Parallel Systems for Performance Prediction. In: Performance Evaluation of Parallel Systems (PEPS'93), 1993-11-01, Warwick.

Clarke, C. T., 1993. The Implementation and Applications of Multiple-Valued Logic. Thesis (Doctor of Philosophy (PhD)). University of Warwick.

Nudd, G. R., Atherton, T. J., Kerbyson, D. J., Clarke, C. T., Papay, Y., Papaefstathiou, E., Ziani, R. and Zemerly, J., 1993. Assessing the Performance of Parallel Computers - PEPS (ESPRIT 6942). In: 2nd Workshop on Abstract Machine Models for Highly Parallel Computers, 1993-04-01, University of Leeds, Leeds.

Summerfield, S., Clarke, C. T. and Nudd, G. R., 1992. VLSI arithmetic with current mode multiple valued logic. In: IEEE International Symposium on Circuits and Systems (ISCAS '92), 1992-05-10 - 1992-05-13, San Diego, CA.

This list was generated on Fri Oct 24 15:44:26 2014 IST.